1. Field of the Invention
The present invention relates to an apparatus and method for reliably testing and installing individual integrated circuit chips using die adapters that minimize damage to the chips.
2. Description of the Related Art
A semiconductor die (plural “dice”) is an integrated circuit designed to serve a specific function, such as a memory chip, in an electronic device. Dice are generally fabricated together in rows on a silicon wafer. During die fabrication, also known as wafer processing, photolithography is traditionally used to first print an image of the micro-circuitry of each die on a wafer surface, duplicating the circuit image at each adjacent die location until the wafer surface is filled. Subsequent processing often including ion implantation, epitaxial deposition, metallization and polishing result in a finished wafer comprising numerous individual integrated circuit chips. Before use, the chips are generally cut from the wafer and packaged in, for example, multi-chip modules (MCM's) for incorporation into final electronic devices such as computers and cell phones. However, because the yield of a wafer (i.e., the percentage of chips on a wafer that function properly) is often not very high, it is important to determine which chips are defective and which chips are functional before the chips are packaged. Defective die are discarded or repaired so that only functional “known good die” (KGD) are packaged in electronic devices.
Knowing whether a die is a “known good die” before it is packaged is increasingly important as more and more chips are packed into individual MCM's. Otherwise, the compound effect of the individual yields of the different chips can result in very low yields of functioning MCM's.
Determining the yield of a wafer and isolating the KGD's is often performed through batch testing of dice using test probes before the dice are cut from a wafer. The probes are used to conduct “bum-in” tests where the dice are rigorously exercised through various temperature cycles, including high temperatures, and at high potentials. Defective dice are generally expected to fail after a certain number of hours of burn-in testing. A die that passes the tests, and that is subsequently integrated into an electronic device, generally has a high probability of performing properly over the expected life of the device (a phenomenon sometimes referred to as “fail early or never fail”). Examples of such burn-in test procedures performed on uncut wafers are disclosed in U.S. Pat. No. 6,323,663 to Nakata et al.; U.S. Pat. No. 5,701,666 to DeHaven et al.; and U.S. Pat. No. 5,440,241 to King et al.
Sometimes it is not feasible to conduct a final die test before dice are cut from a wafer. Where very high reliability is required, for example in spacecraft electronics, end users of a chip often need to retest an individual cut die after receiving the die from a die manufacturer and immediately before packaging the die in a device or module. Such final testing procedures can be difficult and time consuming and particular care must be taken so that the testing procedure itself doesn't damage an otherwise good die. Traditional procedures require placing a die in a temporary package, testing the die in the package, and then removing the die from the package. These procedures have several inherent problems. First, to be successfully tested in a temporary package, a die often requires enlarged pads, to which the test leads of the package are wire bonded, and the enlarged pads can reduce integrated circuit density. Dies with a small pad pitch, i.e., center-to-center distance between the pads, make it difficult to reliably connect test leads. Second, the bond wires of the test package often need to be broken off and removed from the chips before final packaging. The process of removing bond wires will frequently damage the bond pads of a die. Finally, the above procedures require an excessive amount of die handling that increases the chances of damaging the die.
U.S. Pat. No. 6,353,312 to Farnworth et al. and U.S. Pat. No. 5,571,027 to Roebuck et al. disclose temporary test packages designed to avoid the above mentioned problems concerning testing an individual die. The '312 patent discloses a positioning device for accurately and efficiently placing dice in temporary packages to avoid handling damage. The '027 patent discloses an interconnect system using a socket with spring biased contacts to lock a die in place during testing and to minimize die pad damage during debonding of test leads. Both the '312 patent and the '027 patent disclose complex devices used in high volume chip testing; however more economical methods are needed for low volume testing processes.
Therefore there is a need for an improved, economical and non-destructive method for testing individual semiconductor chips after the chips have been cut from a wafer and before they are assembled in a module.